Researchers at Tokyo Tech have developed a novel full-duplex (FD) communication system that can transmit and receive signals at frequencies over 100 GHz and at a data rate of 112 Gb/s. The proposed architecture is a significant advancement towards meeting the requirements needed for sixth-generation (6G) networks, which are expected to offer data rates of over 100 Gb/s and low latencies for applications like virtual reality and autonomous cars.
The Advantages of a Full-Duplex Architecture
The FD architecture enables a single system to transmit and receive signals, effectively doubling the throughput. One way to implement this architecture is to make the transmission and reception modules share a single antenna, reducing the circuit’s size and allowing both parts to make full use of the available frequency spectrum.
The Self-Interference Challenge
However, single-antenna FD architectures suffer from self-interference (SI), where the transmitted signal leaks into the receiver side, which leads to poor signal quality. Such systems include circuits for SI cancellation that attempt to cancel the generated SI by injecting an equal signal with the opposite polarity. Implementing effective SI cancellation is much more challenging in the sub-THz band than in lower frequencies, which remains a hurdle to single-antenna FD designs.
A Novel Full-Duplex Communication System
The research team of Professor Kenichi Okada at Tokyo Tech has developed a novel FD communication system addressing the obstacles posed by SI. The team presented their design at the 2023 Symposium on VLSI Technology and Circuits held in Kyoto, Japan.
The system’s main feature is the implementation of a dual-polarized patch antenna driven by differential signals – a combination of positive and negative feeding ports for transmission and reception. By making the circuit paths of these ports highly symmetrical, the mismatch of the transmitted signal that leaks into the differential receiver’s ports is minimized, which helps keep SI low.
Another critical aspect of the proposed design is the SI cancellation (SIC) circuit. For effectively canceling the generated SI, one needs to modify the phase of the cancelation signal carefully. This is usually done using variable capacitors called varactors. However, at the sub-THz range, conventional varactors have a limited phase range and poor resolution. To tackle this problem, the researchers developed a new varactor structure that achieved excellent linear resolution over the entire sub-THz band and over the full 360° range.
Promising Results
The team tested their design through a series of experiments that yielded quite promising results. The proposed FD transceiver achieved 6 Gb/s in over-the-air measurements. The SI suppression was improved by 20 decibels when the SI canceler was turned on. The device, the world’s first FD phased-array transceiver to operate at over 100 GHz, also achieved a data rate of 112 Gb/s in HD mode, making it the fastest-to-date system among sub-THz phased-array transceivers.
The proposed architecture represents a significant advancement towards the telecommunications technology required for 6G. With a compact size and a wide range of operating frequencies, this new transceiver design could pave the way for more advanced technologies in the future.
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